Semiconductor Engineering

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification

“This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD ...
Seeking Alpha

Silvaco Expands its Victory TCAD and Digital Twin Modeling Platform to Planar CMOS, FinFET and Advanced CMOS Technologies

SANTA CLARA, Calif., Sept. 24, 2024 (GLOBE NEWSWIRE) -- Silvaco Group, Inc. (SVCO) (Nasdaq: SVCO, “Silvaco” or the “Company”), a provider of TCAD, EDA software, and SIP solutions that enable ...
EDN

Synopsys Tackles 45nm Process-Related Variation

Revealing another piece of its DFM tool arsenal, Synopsys Inc. today detailed its new process-aware design-for-manufacturing (PA-DFM) tools, meant to analyze variability effects at the custom/analog ...
EDN

IMEC Reports Possibility of Sub-45nm CMOS Scaling

At the IEEE International Electron Devices Meeting (IEDM) today, Belgian research center IMEC detailed a simple CMOS integration scheme of a NiSi gate for NMOS and a Ni2Si gate for PMOS on HfSiON with ...
TechRepublic

Intel’s 45nm CMOS Technology Performance Parameters in VLSI Design

The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. In this paper, the authors describe Intel’s 45nm technology ...
Electronic Design

Alliance Produces Ultra-Dense SRAM Cell In 45nm CMOS Technology

The Crolles2 Alliance has described at the VLSI Symposium in Kyoto, Japan, the creation, under production conditions, of six-transistor SRAM-bit cells with an area less than 0.25 square microns?half ...