Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

VLSI or Very Large Scale Integration has emerged as a crucial field in electronics engineering over the past few years. With the manufacture of complex integrated circuits (ICs) with millions of ...

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...

Hierarchical test is a methodology that lets you perform most of the DFT work at the block level instead of at the flattened top level of the design. It is not a new approach. In fact, I’ve seen ...

Traditional IC pattern-generation methods focus on detectingdefects at gate terminals or at interconnects. Unfortunately, a significantpopulation of defects may occur within an IC's gates, or cells.

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the ...