Business Wire

MathWorks Speeds Up FPGA-in-the-Loop Verification

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with ...
New Electronics

MathWorks enhances range with fpga and asic coding and verification products

In a move described as a 'significant enhancement' to its product range, MathWorks has launched HDL Coder, which allows HDL code to be generated directly from MATLAB and used to implement fpgas and ...
New Electronics

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Microsemi has announced a collaboration with MathWorks to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...