Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to ...

Asynchronous, or clockless, logic–an alternative to standard digital circuits that avoids many of their problems–is beginning to look attractive for embedded designs in consumer electronics and mobile ...

At 0.18 micron and below, handling crosstalk becomes a significant design challenge. Historically safe and pervasive design techniques may now increase crosstalk, and must be reviewed for suitability.