Guru3D

AMD Zen 6 Architecture Surfaces With 8-Wide Dispatch and 512-Bit Vector Support

AMD’s next-generation Zen 6 CPU architecture has quietly made its first appearance through an internal developer document, ...
Electronics Weekly

riscvOVPsim gets Risc-V vector instructions

Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...
ExtremeTech

ARM guns for high-performance computing with its new vector instruction set

ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...
Geeky Gadgets

RISC-V Vector Processing: A New Era in Computing Efficiency

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
Design-Reuse

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
Electronics Weekly

riscvOVPsim reference model enhanced for vector instructions

Imperas’ riscvOVPsim RISC-V reference model and simulator has been updated and extended for RISC-V vector instructions and now supports coverage driven verification analysis. The base version of ...
ExtremeTech

ARM guns for high-performance computing with its new vector instruction set

ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...