EDN

Electroglas rolls out test handler for wafer-level packages, known-good die

MUNICH — Electroglas Inc. today at the Semicon Europa trade show here introduced a new test-handling solution for devices in wafer-level packages, unpackaged known-good die products, thin wafers, ...
Semiconductor Engineering

Wafer Probe Struggles To Adapt To Multi-Die Assemblies

Delicate features, uneven surfaces, and extreme density make it difficult to manage probe force and ensure reliability.
EDN

TEL debuts handler for wafer-level packages, KGD

TOKYO–Japan's Tokyo Electron Ltd. (TEL) announced Monday (April 12) that it will begin sales of a test handler that supports wafer-level packages and known-good die (KGD) products. Current process ...
Nasdaq

Aehr Receives First Order for FOX(TM) Wafer Level Test and Burn-in System to be used for Gallium Nitride Semiconductor Engineering and Qualification

FREMONT, CA / ACCESSWIRE / December 14, 2023 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial customer ...
Morningstar

Aehr Test Systems and ISE Labs Announce Partnership on Wafer-Level Test and Burn-in for High-Performance Computing and Artificial Intelligence Processors

FREMONT, CA / ACCESS Newswire / November 3, 2025 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in solutions, today announced a strategic partnership with ISE ...
Semiconductor Engineering

Wafer Test Challenges For Chiplets

In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage.